Power integrity problems are deceptive because they rarely manifest as hard failures in early board spins. A board with marginal decoupling or an undersized bulk capacitor on a 3.3V rail often boots, runs, and passes initial functional tests. The problems show up later: instability under load, intermittent crashes during high-activity cycles, failures in temperature-extreme environments, or EMC test failures right before a product certification deadline.
At the schematic review stage, you cannot simulate IR drop or model the impedance profile of your power delivery network with the precision of a dedicated PI simulation tool. What you can do is catch the structural conditions that commonly lead to power integrity failures: missing bypass capacitors, bulk capacitance below minimums for rail loading, ground return path splits that create inductive loops, and decoupling networks with value ranges outside what a device's datasheet requires.
This article covers the power integrity rule categories in CADY's library, what each one checks, and how to interpret violations when they fire.
Bypass capacitor presence: the most commonly fired rule
The bypass capacitor presence rule checks that each IC power pin has at least one capacitor connected to the same supply net within a specified net distance from the power pin. This is the most frequently violated rule in CADY's default library, and the most valuable one to run before any other power integrity check.
The rule operates at the net level, not at the physical distance level. It cannot determine whether a bypass cap placed on the same net is physically close to the IC's power pin on the board. What it can determine is whether a bypass cap exists on the same supply conductor as the power pin, with no intervening ferrite bead, series resistor, or other impedance element between the cap and the pin.
This is an important distinction. A 100nF bypass cap placed on VCC at the opposite end of the schematic from a 100MHz processor core is a structural miss that the rule catches. A cap placed on the correct side of a ferrite bead when the power pin is on the other side is also a structural miss. Both violate the bypass cap presence rule and both can cause power integrity issues on the board, though for different reasons.
CADY flags these violations. Whether the flagged condition will cause a functional problem depends on the device's switching behavior, the PCB layout, and the load transient characteristics, none of which are in the netlist. Use the violation as a prompt to verify your decoupling strategy for each flagged device, not as a verdict on whether the board will fail.
Bypass cap value range: not all capacitors are equivalent
The bypass cap value range rule checks that capacitors on a supply net fall within a range appropriate for the device's supply pin characteristics. This rule operates against a default value table in CADY's library, which maps common supply voltage levels and IC categories to recommended bypass capacitor value ranges.
The default ranges in the library are conservative: 100nF to 10uF for general CMOS logic, 10nF to 1uF for RF front-end supply pins where larger capacitance increases self-resonant frequency concerns, 10uF to 100uF for power stages with significant load transients. If your design uses a device with specific bypass requirements published in its datasheet, you can configure custom value range rules per component class.
Common violations include:
- 10uF electrolytic placed as the only bypass for a high-frequency digital IC (too high self-resonant frequency for the device's switching noise frequency)
- 1nF ceramic placed as bypass for a logic supply rail (value too low to hold the rail during a current transient)
- Decoupling that passes presence check but fails value range: a 1pF capacitor technically exists on the supply net, but provides no useful high-frequency filtering
Bulk capacitance per rail
The bulk capacitance rule checks that each supply rail has a minimum total capacitance from all connected bulk capacitors (typically electrolytic or large ceramic, value above 10uF). This rule is not concerned with individual bypass caps but with the overall energy storage on the rail for handling load transients.
The check sums all capacitor values above the bulk threshold connected to a supply conductor and compares the total against a minimum. The minimum is configurable per rail name pattern in your project's rule file. CADY's default library uses 100uF as the WARN threshold and 10uF as the CRIT threshold for typical 3.3V and 5V logic supply rails.
This rule generates the most false positives for designs where a regulator's output capacitor provides the bulk capacitance. If the regulator's output cap is on the same conductor as the downstream supply distribution net, the rule correctly counts it. If the regulator and the distribution rail are on separate conductors connected by a short trace (which is often intentional to allow independent measurement points), the rule may fire on the distribution side even though bulk capacitance exists at the regulator output.
Power supply output pin type matching
Every supply rail should have exactly one power output source (a regulator output pin, a power jack, or a battery connector) driving it. The power supply type matching rule checks that each supply conductor has at least one power_output or power_flag pin connected to it, and flags conductors where this is absent.
In KiCad schematics, the PWR_FLAG symbol is used to explicitly mark supply nets that are driven by an implicit power source (a battery connector, a USB VBUS pin, or an external supply that is brought in without a schematic symbol carrying a power_output pin type). Without a PWR_FLAG or equivalent, KiCad's ERC and CADY's connectivity rules both see the supply conductor as having no driver.
This is the cleanest category of power integrity violation: either the supply net has a source, or it does not. Violations here rarely have legitimate exceptions, and the fix is always to add the missing power source symbol or flag.
Ground net fragmentation
The ground net fragmentation rule checks whether the design has multiple disconnected ground conductors. In a single-supply digital design, a fragmented ground net almost always indicates a wiring error: a net naming inconsistency (GND vs. AGND vs. DGND with no intended isolation), a missing junction, or a hierarchical sheet port that was not connected.
In mixed-signal designs, ground fragmentation may be intentional. The rule is configurable to treat certain ground net name combinations as intentionally separated. If your design uses a star-ground topology with AGND and DGND connected at a single point through a bridge component, you can configure the rule to recognize that pattern as intentional and suppress the violation.
Without this configuration, the rule fires on every disconnected ground conductor, which in a mixed-signal design would produce violations on every intentional analog-digital ground split. Configure your known intentional splits before running the full library on a mixed-signal schematic.
Return path continuity at sheet boundaries
In hierarchical schematics, ground return paths must be explicitly carried through hierarchical port connections between sheets. A signal that travels through a hierarchical boundary on its forward path also needs its return path to cross the same boundary. If the ground reference for a signal block on a child sheet is provided by a local power symbol but is not explicitly connected to the parent sheet's ground conductor, the signal can appear connected at the schematic level while the physical return path on the board is routed incorrectly.
CADY's return path continuity rule checks that each hierarchical sheet boundary has at least one explicit ground or low-side net connection crossing it alongside each signal connection. This is a WARN-level violation because some hierarchical designs use implicit global power symbols that satisfy the requirement without an explicit port. The rule fires when no explicit ground crossing is present and no global power symbol on the child sheet resolves to the parent's ground conductor.
Power integrity rules in CADY catch structural conditions that correlate with power delivery problems. They do not predict board-level impedance, IR drop magnitude, or decoupling effectiveness under specific load conditions. A schematic that passes all power integrity rules has met the structural criteria for a reasonable power delivery architecture. Whether it will meet performance requirements under load is a question for post-layout analysis.