Missing decoupling capacitors are the kind of error that slips past the human eye on a first review. The schematic looks clean. The ICs are all connected. Every power rail traces back to the supply. And then the board comes back, and you spend two days debugging erratic behavior on a bus that tests fine in isolation but falls apart under switching load. The missing 100nF cap on VCC was right there in the component datasheet, three lines below where you stopped reading.
This piece explains how CADY's rule engine approaches decoupling cap detection: what it actually checks at the netlist level, where the boundary of the rule sits, and how we represent the result in the violation report.
Why the netlist is the right layer for this check
Decoupling cap rules operate on connectivity, not geometry. At the schematic review stage, placement is not yet locked, but what we can reason about is: does a bypass capacitor appear on the same VCC net as a given IC's power pin? Is the capacitor connected between VCC and GND? Does the capacitor value fall within the range appropriate for the IC's switching frequency?
KiCad's netlist export gives us all three data points. When you export your schematic via File > Export > Netlist and select the KiCad format or the legacy Orcad-compatible format, the resulting file contains a flat component list with pin-to-net mappings. CADY parses that into an internal component graph, where each node is a component instance and edges represent shared nets between pins.
The decoupling cap rule walks this graph. For each IC instance whose datasheet-class implies power consumption above a threshold (micro-controllers, FPGAs, DDR interfaces, high-speed serial transceivers, analog front ends with digital control interfaces), the rule checks whether at least one capacitor is connected between the IC's VCC pin net and a GND net. It checks this per supply rail: a device with separate VCC_IO and VCC_CORE pins needs bypass caps on both.
The structure of the rule predicate
In CADY's rule language, the decoupling cap check is a net-neighborhood predicate. Simplified, it reads: for component C with pin P connected to a power net N, there must exist a passive component Q of type capacitor, with one pin on N and another pin on a GND net, within the same schematic sheet as C, and with a capacitance value not less than a configurable floor.
The configurable floor matters. A 1pF placement cap does not count as bypass decoupling for a 200MHz MCU. Our default floor is 10nF for digital ICs, with a separate rule that flags single-capacitor decoupling where the IC's recommended decoupling specifies both a bulk cap and a high-frequency bypass. You can override both thresholds in a custom rule file if your design uses unusual process nodes or your power rails operate at non-standard voltages where the usual capacitance guidance doesn't apply.
What the rule does not check: it does not verify capacitor placement proximity on the PCB layout, because the netlist does not carry physical coordinates. Proximity is a layout-layer check that belongs in your PCB DRC after placement. CADY's job is schematic-level connectivity and BOM accuracy, not auto-routing or layout verification.
How hierarchical sheets affect the check
Hierarchical designs introduce a complication. In a multi-sheet KiCad project, power symbols like VCC, GND, and VDDA are global nets by default. A bypass cap on sheet 2 will appear on the same net as an IC on sheet 5. That is correct electrical behavior, but from a design review standpoint, the proximity intent is violated: a cap on the analog supply sheet is not providing effective bypass for a DDR controller on the digital board section.
We handle this with a locality option on the rule. When the rule's locality: "sheet-local" flag is set, the checker requires that the decoupling capacitor appear on the same sheet as the IC instance, not just on the same logical net. This is the mode we recommend for any hierarchical design where separate sheets represent physically distinct board regions or voltage domains. For flat schematics, the default net-global mode is sufficient.
The violation report distinguishes between these cases. A net-global miss (cap exists but on a different sheet) gets a WARN severity, because the connectivity is technically correct and the designer may have intended it. A complete absence of any bypass cap on the net gets a CRIT severity, because there is no electrical path for high-frequency decoupling current regardless of placement.
What a real violation looks like in the report
In our early-access program data, missing decoupling caps were the second most common CRIT violation across submitted schematics, after net-no-driver errors. The pattern we saw most often: designers added decoupling to the obvious high-speed devices (MCU, FPGA, DDR) but missed the smaller consumers, such as 3.3V logic on a separate I2C bus controller or a USB Type-C PD controller IC with its own VCC pin that was not in the same schematic template block as the main MCU.
In the report, the violation looks like this:
CRIT PWR-DEC-MISS U12 (PD controller, sheet: USB_PD)
Pin VCC (net: VCC_3V3) has no bypass capacitor on sheet USB_PD.
Net VCC_3V3 has 2 capacitors, both on sheet: PWR_RAIL.
Suggest: add 100nF decoupling cap between VCC_3V3 and GND
co-located with U12 on sheet USB_PD.
Rule: power-decoupling-sheet-local, threshold: 10nFThe violation names the component, the sheet, the net, and the existing cap locations. An engineer reading this can act on it immediately without digging back into the schematic to reconstruct what went wrong.
Bulk capacitance and multi-cap rules
The high-frequency bypass rule is one of three related power integrity checks in this category. The second is bulk capacitance: for power rails driving more than a configurable number of load components, CADY checks that at least one electrolytic or tantalum cap of 10uF or larger is present on the rail. This catches boards where every IC has its 100nF bypass but nobody added a bulk reservoir for the transient load of simultaneous switching.
The third check is value-range coherence. If a bypass cap value is outside the range appropriate for the IC class (e.g., a 10uF ceramic on a high-speed SERDES VCC where the net impedance requirement implies a specific capacitor value range), the rule fires an INFO violation. INFO violations are advisory: they do not block sign-off in our default configuration, but they show up in the report for the reviewing engineer to decide whether the value is intentional.
To be clear about what these three checks cover and what they do not: CADY does not verify that the capacitors will achieve the target power delivery network impedance profile. PDN impedance modeling requires SPICE simulation with parasitics. What CADY flags is the absence or gross misconfiguration of decoupling components at the schematic level. Think of it as a checklist verifier, not a SPICE simulator.
Running the check in KiCad
To run CADY's decoupling cap rules against your KiCad project, export the netlist in KiCad format (.net) from the schematic editor, upload the file to CADY via the web UI or the API, and ensure that the power-integrity rule category is enabled (it is enabled by default for all accounts). The violation report returns within a couple of minutes for schematics up to roughly 500 components on current infrastructure.
If your team has non-standard decoupling requirements (for example, a design targeting an RF-sensitive application where caps below a certain Q factor are not acceptable, or a space-grade design where specific capacitor dielectric types are required), the custom rule authoring interface lets you extend or override the defaults. You can set per-net thresholds, component-class filters, and locality modes independently for each rule instance.
The goal is not to replace the senior engineer doing the final power integrity review. It is to make sure the obvious catches land before that review happens, so the senior engineer's time goes toward the genuinely ambiguous decisions rather than hunting for missing caps on sheets they have not looked at in two weeks.