Most EDA tools ship with a built-in ERC that checks a few dozen net connectivity conditions. CADY's library covers 870+ rules across six distinct categories, each targeting a different class of schematic error. Understanding how those categories differ, and which ones produce the highest-consequence catches, helps you prioritize your review workflow and configure the right severity levels for your project.
This article breaks down CADY's six rule categories, explains what each one examines, and gives a practical sense of which categories matter most for different design types.
Category 1: Net connectivity
Net connectivity rules check the structural integrity of electrical connections. This is the category most EDA tools' built-in ERC covers, though usually with a subset of the checks CADY includes.
Core checks in this category:
- Net-no-driver: a net has receivers but no driver pin
- Pin-type conflict: two pins of conflicting types connected to the same net (two output pins wired together, for example)
- Single-pin nets: a net connected to only one pin, indicating a likely missing connection
- No-connect violations: a pin with a no-connect marker that is actually connected to a net
- Net naming conflicts: multiple nets with the same name on different sheets that resolve to different conductors
Net connectivity violations are the most directly traceable to hard functional failures. A board with a net-no-driver error will either have a floating input or an open output that produces incorrect behavior in all conditions, not just some. These are CRIT-level findings by default.
Category 2: Power integrity
Power integrity rules check the structure of the power delivery network: whether supply rails have appropriate bypass capacitors, whether bulk capacitance meets minimum thresholds, and whether supply nets have exactly one designated power source.
This category catches errors that often survive functional testing in early board spins but cause failures under load, at temperature extremes, or in EMC testing. A microcontroller with missing bypass capacitors on its core supply will often boot successfully from a lab bench bench supply but fail during high-activity firmware execution or when powered from a battery with higher source impedance.
Power integrity rules flag structural conditions at the schematic level. They do not replace power delivery simulation and cannot predict the exact ripple or voltage drop on a rail. CADY identifies that the bypass cap is absent or undersized; a PI simulation tool tells you the resulting impedance profile. For a full walkthrough of each check in this category, including bulk capacitance, ground fragmentation, and return path rules, see Power Integrity Rules in CADY's EDA Review Library.
Category 3: BOM consistency
BOM consistency rules check that component references in the schematic match the expected form for BOM export and procurement. This category addresses a class of errors that is completely invisible in functional testing but causes significant downstream problems in production.
Core checks include: duplicate reference designators (two components with the same R or C designator in the same design), missing manufacturer part numbers (components without an MPN attribute that will require manual lookup during procurement), inconsistent value formats (100nF vs 0.1uF vs 100000pF for the same value type across different components of the same class), and footprint-value mismatches (a 0402 footprint with a value that requires an 0603 case size for the specified capacitance at the rated voltage).
BOM errors are particularly costly in production because they are discovered late. A duplicate reference designator in a design with 300 components is invisible in schematic review and usually invisible in PCB layout. It surfaces when the pick-and-place program generates an error, or when the assembly house returns a query, at which point a board revision cycle may already have been committed.
Category 4: Component footprint matching
Footprint matching rules check that the component instances in the schematic are associated with appropriate footprints for their specified values and package types. This category bridges the schematic and layout domains.
The most consequential checks here are pin count mismatches (a schematic symbol with 8 pins associated with a footprint that has 6 pads), polarity markers (polarized components with footprints that lack pin 1 or anode indicators), and package size constraints (a value or current rating that is physically incompatible with the specified footprint).
Footprint mismatches that survive to the layout stage are hard to catch because the layout engineer works from the netlist and footprint assignment, not from the component's electrical characteristics. A capacitor with an incorrect footprint assignment will be placed and routed correctly according to the layout tools. The error appears when the assembled board has components that do not fit their pads, or more subtly, when a component that physically fits has been assigned a footprint with the wrong pad pitch and appears electrically connected but with insufficient solder joint coverage.
Category 5: Clearance and spacing rules (schematic level)
Clearance rules at the schematic level address net classification constraints rather than physical PCB trace spacing. Physical trace clearances are a layout-level concern that CADY does not check. What the schematic-level clearance category covers is signal classification: high-voltage nets that should not share component packages with low-voltage signal nets, mains potential traces that need physical isolation from accessible conductive surfaces in a product, and creepage distance requirements for safety-critical designs.
This category is most relevant for power electronics and mixed-voltage designs. For a standard 3.3V/5V logic design, clearance rules at the schematic level rarely produce violations. For a design with mains-potential power conversion circuits sharing a PCB with low-voltage digital logic, the clearance rules catch net classification errors that have safety implications.
Category 6: Custom team rules
Custom rules are project-specific checks authored by your team and stored in your project's rule file. These are not violations of universal electrical principles but violations of your team's specific design standards: naming conventions, required component attributes, topology constraints for your product family, or checks derived from errors found in past designs.
Custom rules tend to have the highest signal-to-noise ratio of any category because they encode exactly the things your team has already decided matter for your specific designs. A custom rule written after a board failure from a missing pull-up resistor on an I2C bus will catch the same class of error on every future design that runs the rule. The generic connectivity rules would not have caught it because I2C nets with only open-drain outputs and input pins technically pass the net-no-driver check once the pull-up is missing: the bus will just fail to communicate at runtime.
CADY flags violations according to the rules defined across these six categories. The violation report is an input to the engineer's review process. Not every violation represents a design error: some are false positives from library annotation issues, intentional design choices that the rule cannot distinguish from errors, or conditions that are acceptable in a specific project context. Determining which violations require changes and which can be acknowledged is the engineer's responsibility, not the tool's.
The value of categorization is in prioritization. CRIT violations in the net connectivity and power integrity categories demand immediate attention on every design. BOM consistency violations matter most when you are approaching a production build. Footprint mismatches need to be resolved before layout begins. Custom rules are your team's accumulated institutional knowledge encoded as executable checks.