Altium Designer has its own ERC engine, and if you are already running it, you are catching a class of schematic errors before submission to fab. But Altium's built-in ERC is focused on connectivity and pin type rules as defined in the symbol library. It does not check power integrity heuristics, BOM consistency against component lifecycle data, or cross-sheet decoupling coverage. CADY sits in a different lane: it checks the rules that Altium's ERC does not cover, using the netlist as input.
This guide covers the specific steps for getting a netlist out of Altium in a format CADY can process, submitting it via the API, and incorporating the violation report into your existing review workflow. We also cover the main issues we have seen with hierarchical Altium projects and how to handle them.
Choosing an export format: IPC-2581 vs ODB++
Altium Designer supports several netlist-adjacent export formats. For CADY, two are useful: IPC-2581 and ODB++. A third option, the Altium NetList format, works but is the least information-rich of the three.
IPC-2581 is an XML-based format standardized by IPC for design data transfer to PCB fabricators and assemblers. It contains schematic netlist data, component attributes, and BOM information in a single structured file. CADY's IPC-2581 parser extracts all of these in one pass, which means you do not need to separately export a BOM CSV alongside the netlist.
ODB++ is an older Gerber-replacement format originally developed by Valor. Altium's ODB++ export includes netlist data, but it is more oriented toward fabrication-layer information than schematic connectivity data. CADY can parse the netlist from ODB++ exports, but the component attribute coverage is lower than IPC-2581. We recommend IPC-2581 for new integrations.
To export IPC-2581 from Altium Designer 23 or later: in the PCB editor, select File > Fabrication Outputs > IPC-2581. In the export dialog, set the revision to B (the current production revision), check "Include BOM data" if you want CADY to run BOM checks from the same file, and export to a directory you can access from your CI environment or upload manually.
For a netlist-only export from the schematic editor (without needing an associated PCB file), Altium also supports Design > Netlist > Create Netlist with multiple format options. The Altium netlist format works with CADY but does not include BOM fields. If you use this path, export a BOM separately from Reports > Bill of Materials and submit both files together.
Hierarchical schematics and net naming
Altium's hierarchical design structure handles net naming differently from KiCad. In Altium, hierarchical sheet entries (ports) and sheet connectors (off-sheet references) create logical connections between sheets that are represented in the flat netlist with fully qualified net names. A net named DATA_BUS[0..7] on a top-level bus interface sheet will appear in the flat netlist as individual bits: DATA_BUS0 through DATA_BUS7, with component-pin associations on each.
CADY processes the flat netlist, so hierarchical net expansion happens before the data reaches the rule engine. This is what you want for connectivity checks, but it has an implication for the locality mode of decoupling cap rules: when CADY sees a power net, it cannot infer from the flat netlist alone which sheet a particular capacitor was on. You need to use the IPC-2581 export (which includes sheet association data for components) rather than a flat netlist export if you want sheet-local decoupling checks to work correctly in a hierarchical Altium design.
A specific issue we have seen with Altium hierarchical designs: multi-channel designs where the same sub-sheet is instantiated multiple times. In a 4-channel audio board where the same amplifier circuit is used four times, Altium can be configured to use multi-channel mode, which instantiates the sub-sheet four times with channel-specific reference designator suffixes (U1_1, U1_2, U1_3, U1_4). The flat netlist export correctly differentiates these instances. CADY handles them as separate component instances, which is the correct behavior for BOM counting and per-instance rule checks.
Submitting to CADY
The submission flow is the same as for KiCad exports. CADY's POST /reviews endpoint accepts IPC-2581 files via multipart upload with the field name netlist. If your IPC-2581 file includes BOM data, CADY extracts it automatically. If you are submitting a separate BOM CSV, add it with the field name bom.
A minimal upload using curl:
curl -s -X POST https://api.cadysoiutions.com/v1/reviews \
-H "X-CADY-Key: ${CADY_API_KEY}" \
-F "[email protected];type=application/xml" \
| python3 -c "import sys,json; d=json.load(sys.stdin); print(d['id'])"The type=application/xml hint in the upload tells CADY to expect XML rather than a plain netlist text file. This is optional but prevents the parser from needing to detect the format by inspection, which adds a small latency overhead for large files.
Reading the violation report
The violation report from GET /reviews/{id} returns a JSON object with a violations array. Each violation has: severity (CRIT, WARN, INFO), rule_id (a stable identifier you can reference in your team's rule documentation), component (the reference designator), net (if applicable), sheet (if sheet data was available), and message (human-readable description).
For Altium users, the most useful integration is feeding the violation list into the project's review notes in Altium's Draftsman or into a linked issue tracker. One workflow that has worked well for teams in CADY's early-access program: pull the CRIT and WARN violations into a structured markdown file that lives alongside the project in version control, updated on each review run. That gives reviewers a persistent checklist tied to specific component instances, rather than a transient web report that requires re-running the review to see.
CADY does not write back to the Altium project file. We report violations against the submitted netlist. Fixing the violation means making the change in Altium and running a new review. This is intentional: we are a review tool, not an auto-correction system. Schematic changes should go through the same change control process as any other design modification.
Altium-specific rules to pay attention to
A few CADY rule categories fire more frequently on Altium designs than on KiCad designs, based on patterns in our early-access data.
Power pin type mismatches: Altium's component library has fine-grained pin type definitions (Input, Output, Bidirectional, Passive, Power Input, Power Output). CADY's connectivity rules use these pin types to identify undriven nets. If your design uses custom-built schematic symbols where pin types were not set (left as Passive or Bidirectional for everything), the net-no-driver rule may fire false positives. You can suppress these with a per-rule exclusion in your CADY configuration, but the better fix is correcting the pin type assignments in the symbol library.
Net label scoping: Altium has two types of net labels: sheet-scoped (default) and global. If a net label is sheet-scoped on sheet A and the engineer adds the same label on sheet B expecting a connection, the connection is not made, but the flat netlist will appear to have two disconnected nets with the same logical name. CADY flags these as potential net naming conflicts at INFO severity. They are worth reviewing because they can indicate an actual connectivity error where the designer intended a global connection.
What CADY does not check in Altium projects
CADY does not verify that your Altium project's PCB constraints (clearance rules, plane assignments, impedance-controlled routing specifications) are consistent with the schematic. Those checks run in Altium's PCB design rule check engine against the layout. CADY operates at the schematic-and-netlist level, before layout is done.
CADY also does not check SPICE simulation correctness, signal integrity predictions, or thermal analysis. If your team uses Altium's simulation features, those outputs are separate from the netlist export that CADY processes.
The division is: before layout, before fab, at the schematic stage. That is where CADY adds the most value, catching the structural and BOM errors before they compound with layout decisions. After the board is in layout or after fab files are submitted, CADY's input window has passed.