EDA Design Rule Checking

Catch board-killing errors before the schematic reaches fab.

CADY reviews your netlists and BOMs against thousands of design rules the way a senior engineer would, flagging the costly mistakes early so a bad board never gets manufactured.

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870+
design rules covered
~94%
pre-fab catch rate across 50+ beta schematics
under 2 min
per review on a typical 200-component schematic
The Problem

A re-spin costs $5,000 to $50,000 and weeks of delay

Manual schematic review is slow, depends on whoever is available, and misses subtle connectivity issues that only surface at board bring-up. By then, it is too late.

  • Net driver conflicts go undetected until the board powers on
  • BOM footprint mismatches discovered during assembly
  • Missing decoupling caps cause power rail instability in production
  • CADY catches all of these before the Gerbers leave your workstation
See How CADY Works
How It Works

Three steps from schematic to violation report

No integration required to start. Upload your netlist file and get annotated results in minutes.

01 /03
Upload your schematic or netlist

Support for KiCad, Altium Designer, Autodesk Eagle, raw SPICE netlists, and CSV BOM files. Drag and drop or use the REST API.

02 /03
CADY runs the rule engine

870+ design rules check net connectivity, power integrity, BOM accuracy, component footprint alignment, clearances, and any custom rules your team defines.

03 /03
Receive your annotated violation report

Every violation flagged with severity, the rule that triggered it, the affected net or component, and a plain-English explanation. Export as PDF, JSON, or CSV.

Rule Coverage

870+ rules across six engineering domains

Built from years of real PCB post-mortems and community design review data. Updated with every release.

Power Integrity
180+ rules: supply rail drivers, decoupling placement, bulk capacitance, ground star topology
Net Connectivity
210+ rules: unconnected pins, net driver conflicts, differential pair balance, impedance annotations
BOM Consistency
150+ rules: footprint vs BOM mismatch, reference designator gaps, obsolete part flags
Component Footprint
120+ rules: land pattern vs datasheet, courtyard overlap, thermal pad annotations
Clearance Rules
90+ rules: copper-to-edge, minimum annular ring, drill-to-pad, hi-voltage creepage
Custom Team Rules
Unlimited on Pro and Team: define predicates in our rule DSL, apply company-specific standards
Early Access Feedback

What hardware engineers say

"We caught a missing decoupling cap on the main MCU VDD rail before the Gerbers went to the fab. That one catch alone would have cost us a full re-spin. CADY flagged it on the very first upload."

AR
Amos Reuven
Senior Hardware Engineer, consumer electronics firm (early-access pilot)

"Our team was doing schematic review in spreadsheets before this. Now we run CADY on every revision commit. The BOM footprint mismatch rules alone have saved us two assembly mistakes this quarter."

PS
Priya Sundaram
EE Lead, IoT startup (beta program participant)
Free: 3 reviews/mo Pro: $79/mo, unlimited Team: $249/mo, 5 seats

Start your first free review today

No credit card. No integration setup. Upload your netlist and see results in under two minutes.

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